Portfolio · The Stack
Eric Chen
Full-stack engineer — literally.
From 45nm CMOS cells to production APIs.
From 45nm CMOS cells to production APIs.
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Now — Current Work
What I'm building
spring 2026
Training AI Models on Large Codebases
Python · PyTorch · Transformers · CUDA
Training language models on large-scale codebases for code understanding and generation. Distributed training runs, eval harnesses, the whole deal.
Parallel MCCFR — NLH Poker Solver
CUDA C++ · OpenMP · A100 GPUs
CUDA C++ implementation of External-Sampling MCCFR (CFR+) for No-Limit Texas Hold'em. GPU-batched self-play to train Nash equilibrium strategies.
This site
Next.js · TypeScript · Canvas · Zero dependencies
Iterating on a portfolio that visualizes the hardware-software stack — every layer has a live animation that shows what's actually happening at that abstraction level.
open to:Systems EngHardware DesignML InfraResearch roles
L7 — Application Layer
Software Engineering
where humans meet systems
Production APIs, full-stack apps, and ML pipelines — the surface where commands enter the machine.
MUJI USA — Backend Intern 2025
Python · REST APIs · PostgreSQL · WMS Integration
Built REST APIs syncing e-commerce orders with the WMS — cut p95 order-sync latency 42% across NYC stores. Optimized inventory/allocations queries (3.1× faster, 61% p99 cut). Built idempotent consistency checks and daily data integrity jobs that blocked 1.3k+ bad records/month.
Rankify
React · Node.js · Java · SQL · WebSockets
Social web app to rank Spotify songs with friends. Real-time chatrooms via WebSockets with a multithreaded Java backend, rating system, leaderboards, and full auth flow.
Game Resource Detection — YOLOv11
Python · PyTorch · YOLOv11 · OpenCV
Custom dataset in Roboflow, trained YOLOv11 for in-game resource detection. Deployed as a real-time overlay for automated gameplay workflows.
L6 — Network Layer
Systems & Networking
where bits find their destination
Packets, protocols, and the infrastructure connecting systems. Built from scratch to understand what abstractions hide.
Makeshift IP Router
C/C++ · Linux Networking · LPM
Custom IP router built from scratch — LPM routing table, ARP cache, ICMP handling, and raw packet I/O. Built to understand what the kernel normally hides.
Networking TA — USC
TCP/IP · Routing Protocols · Sockets · Threads
Teaching routing protocols (BGP, OSPF, RIP), socket programming from raw BSD sockets up, and multithreaded server design. Office hours for 80+ students.
L5 — Compilation Layer
Languages & Toolchains
where intent becomes instruction
The bridge between human-readable source and machine-executable binary — lex, parse, IR, optimize, codegen.
Systems & Low-Level
C · C++ · Rust · x86-64 ASM · RISC-V ASM
Manual memory, ownership models, and writing code where the compiler output actually matters. From POSIX sockets to bare-metal startup code.
Hardware Description
SystemVerilog · Verilog · VHDL
RTL design and simulation — clocked pipelines, FSMs, and standard cell synthesis. Targeting FPGAs and ASIC flows.
Scripting & Web
Python · JavaScript · TypeScript · Bash
Python for tooling, ML pipelines, and simulation scripting. TypeScript/Next.js for full-stack. Bash for everything that should have been automated already.
Intel Pin Instrumentation
Intel Pin · C++ · x86 ISA
Binary instrumentation for instruction-level profiling. Used for microarchitecture analysis in gem5 branch predictor research.
L4 — Computer Architecture
Microarchitecture
where instructions become computation
Out-of-order pipelines, branch prediction, cache hierarchies — the machinery that executes the ISA faster than the ISA specifies.
gem5 Branch Predictor Research
gem5 · C++ · Python · SPEC CPU
Implemented TAGE-SC-L branch predictor. Analyzed prediction accuracy and IPC sensitivity across SPEC benchmarks.
Microarchitecture Analysis
C++ · Perf · Hardware Counters
Cache miss rates, branch misprediction penalties, IPC characterization using hardware performance counters.
L3 — RTL / Digital Logic
FPGA & HDL Design
where logic becomes hardware
Clocked state machines, synchronous pipelines, and digital logic running at real frequencies on real programmable silicon.
FPGA Battleship at 100 MHz
Verilog · Artix-7 · Vivado · VGA
Multi-FSM design: game logic, VGA controller (640×480), PS/2 keyboard. All timing constraints met at 100 MHz on Artix-7.
Digital Design Coursework
SystemVerilog · Vivado · ModelSim
Pipelined ALU, UART, synchronous FIFO, clock domain crossing. Timing closure and functional simulation.
L2 — Circuit Design
Analog & Mixed-Signal
where electrons become logic
CMOS standard cells, op-amp topologies, and the analog world underlying every digital abstraction.
TRY THE ADDER →
A (0–15)
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B (0–15)
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CMOS Standard Cell Library
SPICE · Cadence · TSMC 45nm PDK
Full standard cell library: NAND, NOR, XOR, D flip-flop, full adder. Extracted parasitics, verified timing arcs.
Systolic Array
Cadence Virtuoso · SPICE · Custom IC
Designed for matrix multiplication. Matrix A flows east, B flows south, each PE performs a MAC — same dataflow as Google's TPU. Full custom IC in Cadence Virtuoso: schematic, layout, DRC/LVS, parasitic extraction, post-layout timing.
L1 — Transistor Physics
Semiconductor Devices
where physics becomes computation
Drift-diffusion, inversion layers, threshold voltage — the physics making every abstraction above possible.
MOSFET Characterization
SPICE · Device Physics
NMOS/PMOS characterization: Vth extraction, gm/ID design methodology, short-channel effects, velocity saturation.
Personal — Interests
Outside the stack
the non-technical side
Poker — NLH & PLO4
Working through GTO solver outputs (GTOWizard) and range construction. The PLO4 constraint rewards combinatorial thinking. Jane Street puzzle energy.
Puzzles & Problem Sets
Jane Street monthly puzzles, competitive programming, and the occasional AoC. Enjoy problems where the elegant solution is orders of magnitude faster than brute force.
The Showdown — Live Tournament
Recently attended The Showdown poker tournament. Live poker adds a layer the solvers can't fully capture — physical tells, table dynamics, real-time range adjustments under pressure.
End of stack trace
Let's build something.
From bare silicon to production — I work across the full stack, literally.